XETK-S16.0D-M

Defines the type of the microcontroller used in the ECU.

Defines the frequency used for the JTAG interface.

The ETK waits this amount of time, after initiating a JTAG block transfer, before reading the data from the microcontroller. The value is dependent on the JTAG clock speed and the access time of the memory where the data is stored (e.g. DDR vs SRAM).

When ResetOut signal is used, JTAG Initialization Reset Delay [us] should be 0.

This ETK always monitors the Reset signal to determine the microcontroller’s reset status. This feature determines if the ETK additionally monitors the ResetOut signal to determine the microcontroller’s reset status.

Selects the polling rate in μs. Typically at least twice as fast as the fastest raster in a measurement.

Selects how the XETK controls the ECU watchdog.

• Controlled by ECU: The XETK will not drive the signal.
• Enabled: Enables watchdog control from the XETK debugger connector. The XETK will drive the signal as configured to enable the watchdog when the debugger requests the watchdog to be enabled.
• Disabled: The XETK will drive the signal as configured to disable the watchdog.

Controls which level of the watchdog disable signal shall disable the watchdog.

• Low: Low level shall disable the watchdog.
• High: High Level shall disable the watchdog.

The ETK has the ability to wake up the ECU by applying voltage to the CalWakeUp pin of the ECU connector. This makes it possible to download the content of the working page and configure a measurement while the ECU is off.

When waking up the ECU via the CalWakeUp pin it can be selected whether the pin is pulled until the microcontroller core voltage (VDDP) is high or whether the pin should be kept on high state until the start-up handshake between ECU and ETK signals to the ETK that the ECU has finished its initialization.

• YES: The CalWakeUp pin will be kept on high state until the start-up handshake between ECU and ETK signals to the ETK that the ECU has finished its initialization.
• NO: The CalWakeUp pin is pulled until the microcontroller core voltage (VDDP) is high.

Selects the voltage the ETK will use for ECU power supply supervision.

Selects the voltage the ETK will use for ECU standby RAM (working page) power supply supervision.

Selects the ECU bus voltage or lets the XETK device detect the voltage.

The XETK device will drive the data bus of the ECU using the voltage level according to the selected entry.

Selects the standby voltage the ETK will provide to the ECU for the working page.

Selects the signal the ETK will use for ECU standby RAM (working page) power supply supervision.

• ETK Standby Supply: ETK is monitoring the standby supply it provides to the ECU.
• ECU Standby Supply: ETK is monitoring the ECU standby supply; the ECU is not using the standby supply from the ETK.
• No Standby Supply: ETK is monitoring the standard ECU power supply; the working page is not using a standby supply.

Defines the hardware handshake timeout in case the ECU did not perform or does not support a hardware handshake.

To force the ECU to perform the handshake, enter -1 (infinite).  Using this setting, measurement and calibration is only possible if the ECU performs the specified handshake type.

Otherwise enter a value between 0 and 65534 ms.  The value should be set to the earliest time the XETK should access the ECU memory after the ECU is running (both powered and out of reset).

Selects how many register triggers are polled by ETK. All options support multicore systems, however all cores must be able to write to Core 0 registers. Polling will utilize interface bandwidth, and in combination with polling rate, may reduce total measurement throughput:

• Core 0, 32 bits: ETK polls 1 register trigger of Core 0. 32 HW triggers can be used.

• Core 0, 64 bits: ETK polls 2 register triggers of Core 0. 64 HW triggers can be used.

• Core 0, 96 bits: ETK polls 3 register triggers of Core 0. 96 HW triggers can be used.

• Core 0, 128 bits: ETK polls 4 register triggers of Core 0. 128 HW triggers can be used.

• Core 0, 160 bits: ETK polls 5 register triggers of Core 0. 160 HW triggers can be used.

• Core 0, 192 bits: ETK polls 6 register triggers of Core 0. 192 HW triggers can be used.

• Core 0, 224 bits: ETK polls 7 register triggers of Core 0. 224 HW triggers can be used.

• Core 0, 256 bits: ETK polls 8 register triggers of Core 0. 256 HW triggers can be used.

Defines how the XETK shall behave if an overload occurs during data processing.

• Drop Data and Continue Measurement: The XETK drops measurement data, sends an error event and continues measurement.
• Stop Measurement: The XETK stops the measurement and sends an error event.

The location of the structure used for RAM based handshake and triggering. Offset 0x00 is a 32 bit word for ETK to ECU handshake information. Offset 0x04 is a 32 bit word for ECU to ETK handshake information. Offset 0x08 is the 32 bit word for triggering (data acquisition). The base address should be 32 bit aligned.

Defines if the logical handshake is used.

Defines the location of the logical handshake.

• For "Interface Type = PCIe", this field is an offset into the ETK BAR0 memory.
• For "Interface Type = JTAG", this field is an absolute address in ECU memory.

The ETK waits this amount of time (in ms), after recognizing the ECU is out of reset, before writing to the Handshake Mailbox Address.

• For "Interface Type = PCIe", this value is typically 0.

• For "Interface Type = JTAG", this field depends on the boot time for each logical ECU.

Defines if the ETK shall communicate with the ECU via JTAG or via PCIe.