FETK-T3.0A

Defines the type of the microcontroller used in the ECU.

Defines the frequency used for the JTAG interface.

When ResetOut signal is used, JTAG Initialization Reset Delay [us] should be 0.

This ETK always monitors the Reset signal to determine the microcontroller’s reset status. This feature determines if the ETK additionally monitors the ResetOut signal to determine the microcontroller’s reset status.

Selects the polling rate in μs. Typically at least twice as fast as the fastest raster in a measurement.

Selects how the XETK controls the ECU watchdog.

• Controlled by ECU: The XETK will not drive the signal.
• Enabled: Enables watchdog control from the XETK debugger connector. The XETK will drive the signal as configured to enable the watchdog when the debugger requests the watchdog to be enabled.
• Disabled: The XETK will drive the signal as configured to disable the watchdog.

Controls which level of the watchdog disable signal shall disable the watchdog.

• Low: Low level shall disable the watchdog.
• High: High Level shall disable the watchdog.

The ETK has the ability to wake up the ECU by applying voltage to the CalWakeUp pin of the ECU connector. This makes it possible to download the content of the working page and configure a measurement while the ECU is off.

When waking up the ECU via the CalWakeUp pin it can be selected whether the pin is pulled until the microcontroller core voltage (VDDP) is high or whether the pin should be kept on high state until the start-up handshake between ECU and ETK signals to the ETK that the ECU has finished its initialization.

• YES: The CalWakeUp pin will be kept on high state until the start-up handshake between ECU and ETK signals to the ETK that the ECU has finished its initialization.
• NO: The CalWakeUp pin is pulled until the microcontroller core voltage (VDDP) is high.

Selects the voltage the ETK will use for ECU power supply supervision.

Selects the voltage the ETK will use for ECU standby RAM (working page) power supply supervision.

Selects the ECU bus voltage or lets the XETK device detect the voltage.

The XETK device will drive the data bus of the ECU using the voltage level according to the selected entry.

Selects the standby voltage the ETK will provide to the ECU for the working page.

Selects the signal the ETK will use for ECU standby RAM (working page) power supply supervision.

• ETK Standby Supply: ETK is monitoring the standby supply it provides to the ECU.
• ECU Standby Supply: ETK is monitoring the ECU standby supply; the ECU is not using the standby supply from the ETK.
• No Standby Supply: ETK is monitoring the standard ECU power supply; the working page is not using a standby supply.

Defines the hardware handshake timeout in case the ECU did not perform or does not support a hardware handshake.

To force the ECU to perform the handshake, enter -1 (infinite).  Using this setting, measurement and calibration is only possible if the ECU performs the specified handshake type.

Otherwise enter a value between 0 and 65534 ms.  The value should be set to the earliest time the XETK should access the ECU memory after the ECU is running (both powered and out of reset).

Selects how many register triggers are polled by ETK. All options support multicore systems, however for those which only Core 0 is read, all cores must be able to write to Core 0 registers:

• Core 0, 32 bits: ETK polls 1 register trigger of Core 0. 32 HW triggers can be used.
• Core 0, Core 1 and Core 2, 32 bits: ETK polls 1 register trigger per core. The result is combined into 32 HW triggers (that's an option for multicore system where other cores cannot write to Core 0 registers).
• Core 0, 64 bits: ETK polls 2 register triggers of Core 0. 64 HW triggers can be used.
• Core 0, 96 bits: ETK polls 3 register triggers of Core 0. 96 HW triggers can be used.
• Core 0, 128 bits: ETK polls 4 register triggers of Core 0. 128 HW triggers can be read.
• Core 0, 160 bits: ETK polls 5 register triggers of Core 0. 160 HW triggers can be read.
• Core 0, 192 bits: ETK polls 6 register triggers of Core 0. 192 HW triggers can be read.
• Core 0, 224 bits: ETK polls 7 register triggers of Core 0. 224 HW triggers can be read.
• Core 0, 256 bits: ETK polls 8 register triggers of Core 0. 256 HW triggers can be read.

Defines how the XETK shall behave if an overload occurs during data processing.

• Drop Data and Continue Measurement: The XETK drops measurement data, sends an error event and continues measurement.
• Stop Measurement: The XETK stops the measurement and sends an error event.

Determines how the microcontroller’s Nexus Trace port is configured in case of microcontroller FIFO overruns.

• Yes: The microcontroller will stall or delay to avoid trace FIFO overruns.
• No: The microcontroller will not stall or delay to avoid trace FIFO overruns. If the microcontroller software causes a trace FIFO overrun the microcontroller Trace data stream will be missing messages. To use trace triggering it must be guaranteed in microcontroller software to avoid trace FIFO overruns.

In case Stalling on TraceOverrun is enabled, the microcontroller starts stalling when FIFO fill level (%) is greater than enable threshold and it stops stalling when FIFO fill level (%) is lower than disable threshold. This feature defines the FIFO fill level (%) of which microcontroller starts stalling.

Stalling Enable Threshold must always be greater than Stalling Disable Threshold.

In case Stalling on TraceOverrun is disabled, the threshold settings have no effect.

In case Stalling on TraceOverrun is enabled, the microcontroller starts stalling when FIFO fill level (%) is greater than enable threshold and it stops stalling when FIFO fill level (%) is lower than disable threshold. This feature defines the FIFO fill level (%) of which microcontroller stops stalling.

Stalling Enable Threshold must always be greater than Stalling Disable Threshold.

In case Stalling on TraceOverrun is disabled, the threshold settings have no effect.

Sets number of Aurora Lanes used for Trace.

Selects whether Aurora Reset Pin on microcontroller is driven by ETK or not.

Selects the ETK Standby Mode:

• Standard: shorter boot time - higher standby current.
• Deep: longer boot time - minimum standby current

Configures whether the ECU is set into reset during ETK sleep. This may improve the handshake after wakeup.

In case Enhanced Coldstart is used it defines the base address of the Distab Checksum array.

• 0xFFFFFFFF: Enhanced Coldstart is not used.
• Any other value: Enhanced Coldstart is used. The value is the base address of Distab Checksum array.

Defines if Trace Mirror is initialized by ETK. Feature should be set to 'yes' in standard trace configurations, but may be set to 'no' in case of tracing only Display Output Tables.

Selects the order the trace mirror is initialized:

• Set up Trace after writing Coldstart Ready: The trace interface is initialized after writing the coldstart ready pattern. This is commonly used when the ECU project contains large trace windows and is also configured to pre-initialize the ETK trace mirror.
• Set up Trace before writing Coldstart Ready: The trace interface is initialized before writing the coldstart ready pattern. This is a similar sequence used by XETKs.

Selects the behavior of /RDY pin provided to debugger:

• /RDY: Ready output
• /Power-down BIST status: Select this option in case power-down BIST is desired with debugger connected.

Selects how ETK controls /TRST:

• Default: ETK asserts /TRST based on ECU Reset
• Asserted with power-down BIST trigger: ETK asserts /TRST based on ECU Reset and power-down BIST trigger

This feature should be set to "Default" if power-down BIST with ETK connected is not required.

Controls whether data processing shall be continued when a trace overflow occurs.

Defines the method of serial memory access:

• Default: Standard memory access using RH850 “Type A” full access sequence.

• Optimized Block Read: Improves performance by utilizing an optimized RH850 “Type A” access sequence for contiguous/block reads, omitting redundant JTAG IR scans.

• Optimized Scattered Read: Improves performance by utilizing an optimized RH850 “Type B” access sequence for scattered or contiguous/block reads.