XETK-V2.0

Defines the type of the microcontroller used in the ECU.

Selects the JTAG/Nexus Interface Voltage or lets the XETK detect the voltage.

• Auto Detect: The XETK device monitors the JTAG/Nexus Interface Supply Voltage of the ECU and adapts the level used to drive the serial interface lines.
• other entries: The XETK device will drive the JTAG/Nexus Interface lines of the ECU using the voltage level according to the selected entry (e.g. 3.3 V).

Selects the XETK-V2.0A ECU Data bus voltage and the EBI power supply voltage supplied on V_CALBUS. This parameter is not relevant for the XETK-V2.0B.

The default value ("3.3 V") is recommended for all microcontrollers and ECU projects. Before changing this setting, please consult with your local Freescale Semiconductor or ST Microelectronics office to verify the microcontroller’s "2.5 V" data bus compatibility.

Selects the voltage the (X)ETK will use for ECU power supply supervision.

Selects the voltage the XETK-V2.0B will use for ECU standby RAM (working page) power supply supervision. This parameter is not relevant for the XETK-V2.0A.

Defines the hardware handshake timeout in case the ECU did not perform or does not support a hardware handshake.

To force the ECU to perform the handshake, enter -1 (infinite).  Using this setting, measurement and calibration is only possible if the ECU performs the specified handshake type.

Otherwise enter a value between 0 and 65534 ms.  The value should be set to the earliest time the XETK should access the ECU memory after the ECU is running (both powered and out of reset).

Selects the method used for the hardware handshake between the ECU and the XETK, as well as for triggering a data acquisition by the ECU.

• DAI: Microcontroller I/O pins are used for handshake and triggering (Data Acquisition Interrupt).
• Register: Integrated functionality of the debug interface is used for handshake and triggering. No additional microcontroller pins are required.
• RAM: microcontroller internal RAM is used for handshake and triggering. No additional microcontroller pins are required.

Defines the frequency used for the JTAG interface.

Selects the Nexus Trace Clock division factor used by the XETK. The XETK uses a "divide by n" Nexus Trace clock. Trace Clock (MCKO) = System Clock / n.

Selects the chip select used for the XETK.

Selects the data bus width connected to the SRAM on the XETK.

Selects the Nexus Trace port width used by the XETK.

When ResetOut signal is used, JTAG Initialization Reset Delay [us] should be 0.

Defines the delay in milliseconds after ResetOut is released to perform handshake.

Selects how the XETK determines if the microcontroller has completed processing the last JTAG access.

• Pin Available, Block Mode Used: The XETK will monitor the /RDY pin of the microcontroller.
• Pin Not Available, Block Mode Used: The XETK will poll a register of the microcontroller. This should only be used if the microcontroller does not provide the /RDY pin.

(4 byte edit field) Defines base address of the working page memory. The physical address is defined, not the virtual or logical address.

The default value is "0x20000000". If no working page is available the value should be set to "0xFFFFFFFF".

(4 byte edit field) Defines the size of the working page memory.

The default value is "0x00100000". If no working page is available the value should be set to "0x00000000".

Selects how the XETK controls the ECU watchdog.

• Controlled by ECU: The XETK will not drive the signal.
• Enabled: Enables watchdog control from the XETK debugger connector. The XETK will drive the signal as configured to enable the watchdog when the debugger requests the watchdog to be enabled.
• Disabled: The XETK will drive the signal as configured to disable the watchdog.

Determines how the microcontroller’s Nexus Trace port is configured in case of microcontroller FIFO overruns.

• Yes: The microcontroller will stall or delay to avoid trace FIFO overruns.
• No: The microcontroller will not stall or delay to avoid trace FIFO overruns. If the microcontroller software causes a trace FIFO overrun the microcontroller Trace data stream will be missing messages. To use trace triggering it must be guaranteed in microcontroller software to avoid trace FIFO overruns.

The (X)ETK waits this amount of time, after recognizing the ECU is on, before performing the first JTAG initialization.

The (X)ETK asserts ECU reset for the configured delay time and an additionally .5 ms to ensure the complete JTAG initialization is performed while the ECU is in reset.

The XETK-V2.0A monitors V_RESET and the XETK-V2.0B monitors V_NEXUS to determine when the ECU turns on or off.

The (X)ETK waits this amount of time, after recognizing the ECU is in reset, before performing the first JTAG initialization.

The XETK-V2.0 monitors /RESET and optionally /RSTOUT to determine when the ECU is in reset. The delay is required to ensure the JTAG initialization does not start before the microcontroller's internal modules are ready. For example on MPC5777C, delaying until after the device configuration field (DCF) records are finished processing and/or after the built in self test (BIST) is finished executing.

Selects how the (X)ETK controls the JTAG signal /TRST (JCOMP) for JTAG initialization:

• Default: The (X)ETK asserts /TRST for the duration of JTAG Initialization Reset Delay. It occurs on /RESET and /RSTOUT events (if monitored).
• Asserted with /RESETin: The (X)ETK asserts /TRST for a short pulse only on /RESET events. /RSTOUT has no effect on /TRST control. On MPC5777C for example, debug breakpoints and trace configuration will remain valid through /RSTOUT events.

Determines if the (X)ETK requests a globally coherent access when writing to RAM via JTAG.

• Enabled:

  The (X)ETK requests a globally coherent access when writing to RAM. When the RAM is cached and the cache coherency module is enabled in microcontroller software, the written value will immediately be available to the microcontroller.

• Disabled:

  The (X)ETK does not request a globally coherent access when writing to RAM. If the RAM is cached, the written value may not be visible to the microcontroller until the cache is updated.

Determines which MDO pins of the microcontroller are assigned to the Nexus Trace port, when the microcontroller has multiple sets of MDO pins.

• CAL_MDO:

  If the microcontroller has only one set of MDO pins, the (X)ETK configures the Nexus Trace port to use these pins.

  For microcontrollers on VertiCal base boards, the Nexus Trace port is assigned to the MDO pins routed to the VertiCal connector.

• MDO:

  If the microcontroller has multiple sets of MDO pins, the (X)ETK configures the Nexus Trace port to use the production package MDO pins.

  If the microcontroller has only one set of MDO pins, this setting should not be used.

In case Enhanced Coldstart is used it defines the base address of the Distab Checksum array.

• 0xFFFFFFFF: Enhanced Coldstart is not used.
• Any other value: Enhanced Coldstart is used. The value is the base address of Distab Checksum array.

Defines if Trace Mirror is initialized by ETK. Feature should be set to 'yes' in standard trace configurations, but may be set to 'no' in case of tracing only Display Output Tables.

Selects the polling rate in μs. Typically at least twice as fast as the fastest raster in a measurement.

The location of the structure used for RAM based handshake and triggering. Offset 0x00 is a 32 bit word for (X)ETK to ECU handshake information. Offset 0x04 is a 32 bit word for ECU to (X)ETK handshake information. Offset 0x08 is the 32 bit word for triggering (data acquisition). The base address should be 32 bit aligned.

Defines how the XETK shall behave if an overload occurs during data processing.

• Drop Data and Continue Measurement: The XETK drops measurement data, sends an error event and continues measurement.
• Stop Measurement: The XETK stops the measurement and sends an error event.